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Author Topic: Why are N-type silicon semiconductors used in computer chip manufacture?  (Read 3044 times)

Offline RyanGuyardo

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Why n-type Silicon semiconductor is normally used as a subtrate for IC semiconductor in manufacturing?

If possible, paste the related links here too. thanks load. :)
« Last Edit: 02/10/2009 08:19:30 by chris »


 

Offline graham.d

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Actually Ryan it is usually p-type substrates that are used, with n-wells for PMOS devices and the NMOS devices in the bulk (although the bulk doping plays little part in device characteristics today as most, if not all, modern processes implant the surface to suit; this to the extent that they are referred to as twin well processes). The processes can come with the basic wafers either highly doped, which provide a lower impedance path to ground or lightly doped to provide better device to device isolation. Both have advantages and disadvantages. The use of twin well implanted technology removes the need to control the basic substrate doping for the purpose of controlling device characteristics. It has become a convention to have devices running between Ground and a positive voltage. Although it is not essential to have the bulk of the silicon at ground, it does make for consistancy in design and can reduce packaging complexity in some cases.

Because NMOS devices operate with their bulk connection at the lowest supply, with the n-type source and drain connections at a higher supply voltage, it is conventional to have the p-type bulk at ground and the p-type bulk being an implanted region on the wafer surface of the same doping type (and therefore a simple resistive connection). If n-type silicon were used the this would have to be kept reverse biassed with respect to p-regions so the bulk would have to be at a positive voltage with respect to a p-well in which the NMOS devices would sit. It would all work OK with the PMOS devices now sitting in an implanted n-well region resistively connected to the wafer substrate except now the substrate would all have to be at a positive voltage if we were to maintain our conventions for the logic.

In the early days of MOS technology (before CMOS and even NMOS) it was easier to make PMOS devices and these used to be built on n-type substrates. They had to work at much higher voltages than today and typically the supplies were +5v, 0v and -12v. The circuits ran between -12v and +5v (with the bulk at +5v) with the 0v to allow I/O circuits to communicate with external TTL logic.

No links I'm afraid. This is all out my head. Type in key words to Google; you can probably do this as well as I can.
 

Offline techmind

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Slight diversion:

When I got involved in design of TFT circuits on glass (for display-screens and the like, using CMOS - not standard for LCDs!) we had to make the channels on the N-type transistors twice as wide as the P-type for the same current-carrying capability. Something to do with different mobility in the channel for the two dopings I think.

Can anyone enlighten me? Is there a fundamental reason for this?
« Last Edit: 21/09/2009 22:41:00 by techmind »
 

Offline graham.d

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Yes, techmind, but the wrong way round. Pmos transistors have lower surface mobility because holes have lower mobility than electrons. The difference varies but a factor of betwen 2.5 and 3 is common. It is usually compensated by making the pmos transistors wider.
 

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