[CliffordK (OP)]

I was looking at some of the new solar panels.

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Sunpower has some spectacular efficiency ratings.

22.9% cell efficiency.
20.4% module efficiency.

For the  E20: SPR-333NE-WHT-D solar panel. with a couple of other brands trailing close behind.

But, looking at the cells, they all have the corners chopped off, effectively octagons. 

I presume part of the about 10% difference between the cell efficiency and module efficiency is the holes at the corners of the cells. 

Are the octagonal soiar cells only because the silicon ingots are cast round, and so they are saving silicon?

I've heard that silicon prices have been coming down recently.  How much of the cost of the cells is the raw silicon, and how much is the processing?

I would assume the excess silicon that is trimmed is recycled, and can be cast into new crystals with minimal effort.

Obviously panel efficiency is only one rating, and related to the square footage of the panels.  The other important rating is the cost per watt, as well as the durability of the panels.

I suppose another option would be to lay out the cells in a hexagonal grid.
 
The sides of the array would be a little bit of a problem, but one could use parallel wired half-cells at the top and the bottom, and perhaps equal area trapezoid cells for the sides.

[RD]

Are the octagonal soiar cells only because the silicon ingots are cast round

pulled not cast ... http://en.wikipedia.org/wiki/Czochralski_process

http://en.wikipedia.org/wiki/File:Siliziumwafer.JPG

[Geezer]

I think it's packing density versus silicon area thing. They try to get the maximum silicon area per wafer, but they can't make them round because they would not pack well into arrays, so they make them square, which lets them pack well, but the square extends beyond the area of the silicon at the corners to maximize the use of silicon.

Those familiar with the calculus should be able to figure out the ideal ratio.

[CliffordK (OP)]

I'm not sure if module efficiency is much more than bragging rights in many cases.  However, it may be an effective marketing tool.  Square cells should give a 5-10% module efficiency boost for a minimal cost.  Or, perhaps hexagons as I mentioned above, although they are harder to deal with the edges.  Efficiency can be an issue in some installations.

Circular cells can be staggered, to minimize the loss of space, although edges still would be an issue (perhaps requiring parallel wired half cells as mentioned above).

[graham.d]

As RD says, silicon wafers are sliced from a cylindrical, single crystal ingot so are always circular. They have a small flat on one side which indicates the lattice orientation, but that is not relevent to this.

I think the reason for the Octagon shaping is that someone is making a trade off between making best use of the wafer whilst not having too much non-productive area on the finished array of wafers. i.e you could cut the wafer into squares (and not have any area of the array non-productive) but this would throw away a lot of silicon, or you can pack them as Clifford shows above and have quite a bit of non-productive area on the array. The latter would be most cost effective but I expect it is a key selling point to have more power per square metre.

[CliffordK (OP)]

One other thing.
While one thinks about the big 200 or 300 watt panels. 
There is a huge market for little itty-bitty solar cells. 

So, one could make round cells, cut them into squares, then resell the extra bits to make yard lamps, solar calculators, autonomous toys, and etc.  Perhaps also photodetectors.

[graham.d]

That may be a good idea, Clifford. I don't think photcell technology requires the fine photolithographic techniques used on integrated circuits so there would probably not be a problem with masking, step and repeat patterning etc.

[CliffordK (OP)]

Even with IC's , they make multiple chips out of a single silicon wafer.

With the solar cells, the processing for the entire wafer would be essentially the same, so they could produce the solar cell on a round wafer, then trim it to make multiple large and small cells.  I was thinking the electrode grid would be applied last, but at least the portion of the grid that is painted on could likely be patterned before cutting.

Engineers for small solar equipment might like 20% efficient solar cells, but our current economics probably would preclude paying extra for "premium cells".

I suppose the question is whether the waste from the doping would be more expensive than the waste from the trimming raw silicone, and thus it would determine when in the manufacturing process the wafer would be trimmed.

[Geezer]

Back on the original question, I think it boils down to:

What are the dimensions of the square that encloses the maximum area of a circle?

I was hoping some of our mathematically inclined correspondents might take up the challenge, but apparently, they all ran away.

[graham.d]

Clifford, although multiple device designs can be made on a single wafer, this is not a wholly flexible process. Typically, for a multi-project wafer, the different chip designs are arrayed on to a reticle that is around (say) 25mm square (so up to 25 types each occupying 5mm x 5mm). This reticle is then stepped across the wafer giving a repeat pattern of the 25 chip array. What you are suggesting is that the patterning be different on 4 "edges" of the wafer. This can, and has been, done (in wafer-scale integration) but it is not a common process and requires more manual intervention.

However, I suspect that the required process dimensions for photocells are rather large compared with IC technology so that older technology may be usable which can pattern the whole wafer in one go (projection or proximity aligned to a mask the size of the wafer and photographically produced). I don't know enough about photocell production.

Sawing the wafer would be no problem. There is very little waste. Typically the saw can cut a wafer down a line about 100u wide without damaging the chips either side.

[imatfaal]

Back on the original question, I think it boils down to:

What are the dimensions of the square that encloses the maximum area of a circle?

I was hoping some of our mathematically inclined correspondents might take up the challenge, but apparently, they all ran away.

The actual question is quite different.  The square which has the highest area of silicon is one completely within a circle ie from the centre to the corner is is equal to the radius of the wafer; if the wafer was radius 1 then the square would be side length root 2.  The square with the least amount of wasted silicon water would be the one entirely surrounding the circular wafer - for the unit radius wafer that would be square side of 2. 

To optimise and take up Geezer's challenge you need to decide what is the relative values of wasted silicon (i guess high) versus wasted space in array (I would guess lower)

I have done the calcs and will put them out when I have a sec (these scumbags at my company are acutally insisting I do a bit of work!)

[graham.d]

Yes, exactly, Imatfaal. I am not sure how to reach a conclusion on this. The area efficiency of a panel of photocells is a matter of marketing for specific applications - it may be quite acceptable to use a larger area in many cases, so the value of a smaller area would not have so much value in this case. The cost of the wasted silicon has a defined cost but the trade off between the two is a matter of marketing. 

[SeanB]

I would guess the shape is related to the processing machinery used, more than anything else. Probably the cut off sections are the hold down fingers which held the cells whilst being processed, and they would be cut off and recycled into the raw silicon again. As the cells are going to be placed under a glass cover they would be arranged for maximum packing density irrespective of shape.  This extra spacing will reduce area slightly, but some area will be required for the tabs that connect each cell, and for insulating space between cells. Often cells that are faulty are cut into parts and tested to find the good sections, which are then used to make the cheap solar arrays you find in lawn lights.

[Geezer]

Yes, in retrospect, I was talking complete nonsense. (A first for me!)
 
The most efficient use of silicon would be to use complete circles.

[graham.d]

Sean, the shape of the photocell is always originally circular (minus a small flat deliberately produced to show the crystal orientaion). This is because they are slices of a cylindrical grown single crystal of Silicon; at least this is the case for the photocells described in this thread which are to be used for general electricity generation, rather than specialist small devices for specific light sensing applications. There is a small amount of edge waste on wafers but this can be limited to 2 or 3 mm. The type shown in the picture is not sub-divisable into smaller sections and would rely on an acceptable defect density to yield sufficiently, though there may well be types as you describe.

[imatfaal]

Yes, in retrospect, I was talking complete nonsense. (A first for me!)
 
The most efficient use of silicon would be to use complete circles.

No - not complete nonsense.  There is quite clearly a calculation being made - otherwise cells that look like the one Clifford posted at the very top of the thread would not be made like that.  I am pretty stunned that they are willing to throw away what I thought would be really expensive silicon for the sake of filling the array - I would have thought that rooftop real estate was enormously cheaper than silicon wafer.  But that is clearly not the case - otherwise all units would be (probabably hexagonal) arrays a full disc of silicon.

Reading the spec sheet that Clifford provided - I think the reason for it is a race to higher "efficiency".  If you calculate your efficiency as the panel efficiency rather cell efficiency AND if this is a selling point; then it is possibly worth losing some silicon in order to increase the panel efficiency.
 

[CliffordK (OP)]

Where is the majority of the cost in manufacturing Silicon ingots?
Purifying the silicon?
Pulling the ingot?

It should be possible to trim the ingot into a rectangular block prior to other manufacturing steps, and melt down the waste silicon for reuse with no further purification steps. 

I see the now defunct Evergreen Solar used a String Ribbon method for creating cells that had much less waste, and produced nice rectangular cells, but unfortunately the cell efficiency also suffered.
 
Panel efficiency is important, if one fills the entire sunny portion of the south facing rooftop.  In which case, the higher the efficiency, the more power that is generated. 

Or, for a commercial installation, it determines watts per acreage.

I'd like to add some solar panels to my EV to give myself a nice mid-day boost, in which case, the overall efficiency, or power density, is critical.

[imatfaal]

We want to work out the area of the little area hashed in green (wasted silicon) and the two areas in red (unused space) all in terms of the radius of the circle R and the side of the square 2r  - and then multiply by four.

wasted silicon. this is the area of the wedge formed (between O a b) less the area of the isoceles triangle oab

1. Area of triangle = 1/2 base * height. The base is the chord length between a and b.  The height is the r - half the square side.
1a. What is the chord length - ie between ab? 
Half this distance can be worked out using simple pythagoras - the midpoint (m) of ab forms a right triangle with points o and a. 
oa = R   om = r 
am^2 = R^2 -r^2 
am = Sqrt(R^2-r^2)
1b.Area of triangle = 1/2 base * height.  1/2 base is shown above to be am = Sqrt(R^2-r^2), height is r
Area of trinagle = r(sqrt(R^2-r^2))

2. Area of wedge = 1/2 Angle * radius^2. 
Let's actually calculate the area of the little wedge oam - of angle theta in diagram.
Trig Alert!
2a.Cosine of angle in right triangle is (Adjacent side length = r) divided by (hypoteneuse length=R)
Cos Theta = r/R
Theta = arccos (r/R)
2b. Area of little wedge oam is 1/2 arccos(r/R) * R^2
2c. Area of full wedge is double that ie Area wedge oab is R^2.arccos(r/R)

3. Area of wasted silicon = Area of wedge - Area of triangle

Area of wasted silicon = R^2.arccos(r/R) - r(sqrt(R^2-r^2))


unused area.  This is the area of the quarter square (made by triange with centre o, and top right and bottom right corners) less the amount covered by silicon

1.  Area of quarter square
Area of square = side^2 = (2r)^2 = 4r^2
Area of quarter square = r^2

2. Area covered by silicon. The area of silicon is by observation a quarter circle minus the green sector which is wasted
Area of circle = pi.R^2
Area of quarter circle = 1/4 pi.R^2
Area of segment wasted from above is  = R^2.arccos(r/R) - r(sqrt(R^2-r^2))
Area covered by silicon in quarter of a circle is 1/4pi.R^2 - [R^2.arccos(r/R) - r(sqrt(R^2-r^2))]

2. Area not covered by silicon is Area of quarter square - area covered

Unused Area = r^2 - {1/4pi.R^2 - [R^2.arccos(r/R) - r(sqrt(R^2-r^2))]}


We know have the two areas in terms of the radius and the side length - the next step is to set the radius to 1 (ie the silicon wafer is seen as fixed) and vary the side length.  But I have n urgent meeting at the Windmill Pub on Mill Street (best pies in the country) - so the calculus will have to wait

[graham.d]

I would expect all the subsequent wafer processing to be done prior to trimming the wafer edges off. I think this is likely because all the equipment for wafer processing is designed to handle circular wafers, even though I expect the photcell manufacturers are nothing like state-of-the-art in this respect. So the cost of chopping off bits of the wafer are effectively related to the final processed wafer cost rather than the raw wafer cost. Having said this, the cost of masking, processing and handling for photocell designs is nothing like that of making ICs and I suspect they are probably getting good value by using 150mm diameter wafers that the IC industry hardly uses any more, being on 200mm to 300mm (even some 375). As a result the cost of NOT using all the wafer is not as high as may be thought especially as it only amounts to (in the above pictured example) about 10% of the total available area. In fact 150mm wafers with some preprocessing sell for only about $4 to $5. The cost of connecting up the wafers and putting them in a housing may be much more significant and the benefit of minimising the total area of panelling more attractive.

[graham.d]

Wow, you have got some spare time, Imatfaal. I drew it out on squared paper and estimated it.