[CliffordK (OP)]

It is easy enough to calculate the area of a circular cell, and the area wasted around it by mounting on a square grid, or the area wasted by trimming to a perfect square.  I.E.  Maximum wasted space, minimum wasted silicon, or visa versa.
 [ Invalid Attachment ]
Area of outer square: 4r²
Area if circle: πr²
Area of inner square: 2r²

Wasted space circles on a square grid:
1 - (πr² / 4r²) = 1 - π/4 = 21%

Wasted silicon, cutting squares from circles.
1 - (2r² / πr²) = 1 - 2/π = 36%

[graham.d]

Clifford, the example in the photo you present is neither one or the other of the diagram above, but it is between the two extreme cases.

[imatfaal]

I would expect all the subsequent wafer processing to be done prior to trimming the wafer edges off. I think this is likely because all the equipment for wafer processing is designed to handle circular wafers, even though I expect the photcell manufacturers are nothing like state-of-the-art in this respect. So the cost of chopping off bits of the wafer are effectively related to the final processed wafer cost rather than the raw wafer cost. Having said this, the cost of masking, processing and handling for photocell designs is nothing like that of making ICs and I suspect they are probably getting good value by using 150mm diameter wafers that the IC industry hardly uses any more, being on 200mm to 300mm (even some 375). As a result the cost of NOT using all the wafer is not as high as may be thought especially as it only amounts to (in the above pictured example) about 10% of the total available area. In fact 150mm wafers with some preprocessing sell for only about $4 to $5. The cost of connecting up the wafers and putting them in a housing may be much more significant and the benefit of minimising the total area of panelling more attractive.

  I was very surprised when I read your ideas of pricing - but they fit right into the reality of the design of arrays, and it makes much more sense now.

Wow, you have got some spare time, Imatfaal. I drew it out on squared paper and estimated it.

  I have a very nice job with large periods of downtime interspersed with lunches and drinks

It is easy enough to calculate the area of a circular cell, and the area wasted around it by mounting on a square grid, or the area wasted by trimming to a perfect square.  I.E.  Maximum wasted space, minimum wasted silicon, or visa versa.

As Graham said that is the two limiting cases - the trick is to find the formula for all cases; cos then you can put in your constants for weighting lost silicon and unused area and differentiate the beast - and get a minimum figure.

You can see that the area of wasted silicon is zero when R=r; Arccos of 1 is zero and R^2-r^2 is zero
Area of wasted silicon = R^2.arccos(r/R) - r(sqrt(R^2-r^2))

You will also find that area unused is zero when R=r.sqrt2

[Geezer]

Nice work Matt!  If we can get you up to speed on a CAD program now, you'll really be cooking with gas

[imatfaal]

Nice work Matt!  If we can get you up to speed on a CAD program now, you'll really be cooking with gas

:-)
I tried Dave's diagram editor - it took me twice as long as the entire calculation to get a square, a circle and labels - and then I managed to lose it.  So I gave up - two minutes later my pencil sketches were uploaded; never managed to properly attach them tho.  Is there still a bug about displaying attachments in the text?

[Geezer]

I tried Dave's diagram editor - it took me twice as long as the entire calculation to get a square, a circle and labels - and then I managed to lose it.  So I gave up - two minutes later my pencil sketches were uploaded; never managed to properly attach them tho.  Is there still a bug about displaying attachments in the text?

Yes - I think it's still on his toodoo list.

I was forced into learning a cad program some years back when the patent office rejected my drawings! They actually did me a favor, although it was a pain at the time. With the amazing graphics quality you get these days on PCs for next to nothing, I find I never draw anything on paper now.

I have used the cheapo TurboCADpro for a long time, and it's more than adequate for what I need. It can generate incredible 3-D renderings, so if you like to investigate interesting geometries you might find it helpful. However, be warned - it's also great time-waster!

There is also a thing called freeCAD ( http://www.ar-cad.com/freecad/index.html ) that let's you model, animate and graph dynamic systems. The drawn elements are primitive, but the math and physics behind the simulation are excellent. If you try running the famous three body problem on it, you'll see what I mean.

[syhprum]

I understand that 450mm wafers are the latest thing

[Geezer]

I understand that 450mm wafers are the latest thing

That's almost 18 inches! (woops - maybe I should not have said that.)

Pretty soon they'll be able to measure them in meters.

[CliffordK (OP)]

I understand that 450mm wafers are the latest thing

That's almost 18 inches! (woops - maybe I should not have said that.)

Pretty soon they'll be able to measure them in meters.

Can I get that built up into a single IC?
Just think of the possibilities with and 18" single chip computer.

[Geezer]

I understand that 450mm wafers are the latest thing

That's almost 18 inches! (woops - maybe I should not have said that.)

Pretty soon they'll be able to measure them in meters.

Can I get that built up into a single IC?
Just think of the possibilities with and 18" single chip computer.

There are probably a lot of reasons why you could not, but I suspect defects in the silicon itself would prohibit it.

Graham will be able to give us a better insight.

[CliffordK (OP)]

I've tried the online drawing program a few times.  Am I the only one?  The new version seems to work smoother than the old one, but it still has a few faults.

You simply choose "Save (&exit)", and your drawing returns to the message.  You must still insert it into the message otherwise it will truly be lost.  However, when I was creating the simple diagram above, it managed not to output the middle (rotated square).  I re-drew the whole diagram twice, and still no middle square.  So, I exported to png and attached.

Anyway, I may still use the system for a few quick&dirty drawings, but I'll probably go back to drawing in OpenOffice/LibreOffice, as the online gizmo always seems to be cumbersome.

As far as image attachments.  Simply use the Shift-Alt-S to attach (see notes at bottom of editing page in case you forget). 
Then, go back to "Modify Document" (at top of message NOT AT BOTTOM OF MESSAGE), and insert the image where you want it to show up.

I look forward to your conclusions as the optimal size of a square to cut out of the circle.  My guess is that you will have the two cases I demonstrated above with either 100% circle  & no square, or 100% square and no circle.  If one chooses square corners, one might also choose to oversize the cells slightly, say 1/4" to allow rounded/blunted corners.

Perhaps I'll try to do calcs for hexagons, both just hexagons on circles, and losses around the edges of the panel.

[Geezer]

I look forward to your conclusions as the optimal size of a square to cut out of the circle.  My guess is that you will have the two cases I demonstrated above with either 100% circle  & no square, or 100% square and no circle.  If one chooses square corners, one might also choose to oversize the cells slightly, say 1/4" to allow rounded/blunted corners.

I suspect it's not possible for us to answer that without knowing the real cost of the non-collecting area within a panel.

If customers only care about watts per panel area, there has to be a trade-off between collection efficiency and silicon area.

[SeanB]

I understand that 450mm wafers are the latest thing

That's almost 18 inches! (woops - maybe I should not have said that.)

Pretty soon they'll be able to measure them in meters.

Can I get that built up into a single IC?
Just think of the possibilities with and 18" single chip computer.

Sir Clive Sinclair tried that in the 1980's, and eventually gave up. Even with the best masking and ability to work around defects he was stymied. I think that it could be doable today by using blocks built as FPGA arrays and flash memory, each with an ISP and self test ability, with a common bus set ( along with routing for short hop and longer hops, with some redundancy for broken links) to create a transputer like multicore unit, with built in distributed storage and distributed memory. Power will be a problem, I remember that Sinclair had to make chains of multiple wire bonds across the die to get power into the interior. Would be difficult to get high current in, and decoupling capacitors would be very large devices ( compared to the chip scale devices) and difficult to integrate. You would also have to use a conductive epoxy to bond the slice to a Kovar heat spreader, and would also need to have it inside a hybrid housing on a ceramic substrate to encapsulate. No possibility of a cheap overmold plastic chip carrier, ceramic case, copper lid and a conformal coating on the slice, as you would not be able to keep the bond wires stable otherwise. It probably would cost more than just using the slice to make chips, cut them apart and test, and assemble the tested parts into a hybrid module. It would also allow you to mix different process technologies, and give you less compromise as to thermal issues across the unit. 

[graham.d]

Sean, I and a few others in my company designed the basic memory unit for that very project. As it still may be regarded as proprietry, I will not go into details. The technical problems were mostly solved (including thermal problems) but a significant issue was that the design/production time needed to produce a "special" memory configuration meant that newer memory designs with 4x the capacity per unit area were available before the wafer scale device could become productionised. Access time was rather slow because of the way devices had to be addressed also. It was not a bad idea and quite adventurous as was Sir Clive's way. There could have been a number of interesting spin-offs too, but really the economics did not work out.

There are significant problems with wafer scale devices in general but mostly they are not technically insurmountable. Thermal issues can be managed in various ways on memories and defect problems are already solved by use of redundancy. I think access time is a probably an important issue and, with large wafers, this will involve driving long lines with a high capacitance and resistance or cascading a route of devices to get in and out from the wafer. I think the Sinclair device was only 4" wafers (maybe 6", I don't remember) so was not so bad.

Syphrum, 450mm wafers are not really in production yet (at least I don't think so) but they are being used in development and may well start in some lines this year.